1. Field
Example embodiments disclosed herein relate to memory devices, for example, flash memory devices, for example, to a multi-chip flash memory device and copy-back method thereof.
2. Description of Related Art
Recently, applications of volatile and nonvolatile memories are increasing for mobile apparatuses, for example, MP3 players, personal multimedia players (PMP), mobile phones, notebook computers, personal digital assistants (PDA), and so on. Such mobile apparatuses may require storage units with greater storage capacity in order to provide various functions (e.g., playing motion pictures). To meet this demand there is a scheme of multi-bit package in which pluralities of memory devices are constructed in a single package. A multi-chip package may be helpful to reduce a package size by about half a normal package type by stacking memory chips of the same kind. A multi-chip flash memory device may be composed of two or more chips using individual chip selection signals that are different from each other. A multi-chip flash memory device may also be organized with pluralities of chips sharing the same chip selection signal.
FIG. 1 is a block diagram schematically showing an example architecture for copy-back in a conventional dual-chip flash memory device. Referring to FIG. 1, each of two memory chips 10 and 20 may include a cell array formed of pages, each of which may be a unit of programming and reading. Each memory chip may include page buffers PB1 and PB2 functioning as write drivers during a programming operation or as sense amplifiers during a reading operation. The memory chips 10 and 20 may share a chip selection signal CS, a read enable signal nRE, and/or a write enable signal nWE. The memory chips 10 and 20 may also share an input/output (I/O) bus 30.
FIG. 2 is a timing diagram schematically showing an intra-chip copy-back operation in the conventional flash memory device shown in FIG. 1. A sequence of the copy-back operations may correspond to the reference numerals {circle around (1)}˜{circle around (8)} of FIG. 1. Referring to FIG. 2, the page buffer PB1 may read source data from a source page Page 1 for the copy-back operation ({circle around (1)}). The read source data may be provided to a memory controller 40 by way of the input/output bus 30 shared by the chips ({circle around (2)}). The read source data for copy-back may be stored in a SRAM included in the memory controller 40. The source data stored in the SRAM may be corrected by an algorithm with error correction codes (ECC). The memory controller 40 may re-input the read source data to the first memory chip 10 and loaded into the page buffer PB1 ({circle around (3)}) in order to program the read source data in a target page Page2. The loaded source data loaded in the page buffer PB1 may be programmed into the target page Page2 ({circle around (4)}). Completion of the programming operation is detected through a status check operation conducted by the memory controller 40. The intra-chip inter-page copy-back operation carried out in the first memory chip 10 may also be applicable to the second chip 20 ({circle around (5)}˜{circle around (8)}).
FIGS. 3 and 4 are block and timing diagrams for illustrating an inter-chip copy-back operation in a conventional dual-chip flash memory device. FIG. 3 shows a dual-chip flash memory device with the same organization and function as in FIG. 1, in which a copy-back operation is carried such that a source page is allocated to the first memory chip 10, while a target page is allocated to the second memory chip 20. Source data copied back may be read out, transferred, and/or programmed through the procedure of {circle around (1)}˜{circle around (8)}. An operation in FIG. 3 will be described with reference to the timing diagram shown in FIG. 4. For a copy-back operation from the source page Page1 to a target page Page3, the page buffer PB1 may read source data from the source page Page1 ({circle around (1)}). The read source data may be transferred to the memory controller 40 by way of the input/output bus 30 shared by the chips ({circle around (2)}). The source data processed with error correction by the memory controller 40 may be input to the page buffer PB2 by way of the input/output bus 20 and an input/output line I/O_2 of the second memory chip ({circle around (3)}). The page buffer PB2 may program the source data into the target page Page3 ({circle around (4)}). A copy-back operation from a source page Page2 to a target page Page4 may be carried out through {circle around (5)}˜{circle around (8)} in the same procedure of {circle around (1)}˜{circle around (4)}.
According to such copy-back operations between pages of chips and between chips, an operation for reading the source page and an operation for writing data into the target page from the source page are performed sequentially. Sequential reading and programming operations may prevent data collision while inputting/outputting the source data while sharing the input/put bus 30 by the chips.